|
| MOQ: | 10PCS |
| Price: | NEGOTIABLE |
| Standard Packaging: | 2000PCS/REEL |
| Delivery Period: | 2-3DAYS |
| Payment Method: | T/T, Western Union |
| Supply Capacity: | 8000PCS/WEEK |
74HCT574D 653 NXP Flip Flops The device has clock (CP) and output enable (OE) inputs
1.General description
The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC
2.Features and benefits
Input levels:
For 74HC574: CMOS level
For 74HCT574: TTL level
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Complies with JEDEC standard no. 7 A
Multiple package optionsESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40Cto+85C and from40Cto+125C
|
|
| MOQ: | 10PCS |
| Price: | NEGOTIABLE |
| Standard Packaging: | 2000PCS/REEL |
| Delivery Period: | 2-3DAYS |
| Payment Method: | T/T, Western Union |
| Supply Capacity: | 8000PCS/WEEK |
74HCT574D 653 NXP Flip Flops The device has clock (CP) and output enable (OE) inputs
1.General description
The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC
2.Features and benefits
Input levels:
For 74HC574: CMOS level
For 74HCT574: TTL level
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Complies with JEDEC standard no. 7 A
Multiple package optionsESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40Cto+85C and from40Cto+125C
