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Programmable CAS 128M DDR3 Synchronous DRAM H5TC2G63GFR-PBA

Programmable CAS 128M DDR3 Synchronous DRAM H5TC2G63GFR-PBA

MOQ: 10PCS
Price: NEGOTIABLE
Standard Packaging: 1600PCS/TRAY
Delivery Period: 2-3DAYS
Payment Method: T/T
Supply Capacity: 100800PCS/WEEK
Detail Information
Place of Origin
TAIWAN
Brand Name
SKHYINX
Certification
ROHS
Model Number
H5TC2G63GFR-PBA
Voltage (Volt):
VDD=1.5V & VDDQ=1.5V
Speed:
DDR3-1866 13-13-13
Number Of Words:
128M
Bit Organization:
X16
Density:
2G
Product Family:
DRAM
Highlight:

Programmable CAS DDR3 Synchronous DRAM

,

128M DDR3 Synchronous DRAM

,

H5TC2G63GFR-PBA

Product Description

 

1.Description
The H5TQ2G83GFR-xxC, H5TQ2G63GFR-xxC,H5TQ2G83GFR-xxI, H5TQ2G63GFR-xxI, H5TQ2G83GFRxxL,H5TQ2G63GFR-xxL,H5TQ2G83GFR-xxJ,H5TQ2G63GFR-xxJ are a 2,147,483,648-bit CMOS Double Data
Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large
memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.

2.FEATURES
* This product in compliance with the RoHS directive.
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
9 and 10
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly

8banks
• Average Refresh Cycle (Tcase 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
Commercial Temperature( 0oC ~ 95 oC)
Industrial Temperature( -40oC ~ 95 oC)
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre
Programmable CAS 128M DDR3 Synchronous DRAM H5TC2G63GFR-PBA 0
4.Why choose us?

100% new and originao with Advantage price
High efficiency
Fast Delivery
Professional team service
10 Years Experience Electronic components
Electronic components Agent
Advantage logistic discount
Excellent After-sales Service

products
PRODUCTS DETAILS
Programmable CAS 128M DDR3 Synchronous DRAM H5TC2G63GFR-PBA
MOQ: 10PCS
Price: NEGOTIABLE
Standard Packaging: 1600PCS/TRAY
Delivery Period: 2-3DAYS
Payment Method: T/T
Supply Capacity: 100800PCS/WEEK
Detail Information
Place of Origin
TAIWAN
Brand Name
SKHYINX
Certification
ROHS
Model Number
H5TC2G63GFR-PBA
Voltage (Volt):
VDD=1.5V & VDDQ=1.5V
Speed:
DDR3-1866 13-13-13
Number Of Words:
128M
Bit Organization:
X16
Density:
2G
Product Family:
DRAM
Minimum Order Quantity:
10PCS
Price:
NEGOTIABLE
Packaging Details:
1600PCS/TRAY
Delivery Time:
2-3DAYS
Payment Terms:
T/T
Supply Ability:
100800PCS/WEEK
Highlight

Programmable CAS DDR3 Synchronous DRAM

,

128M DDR3 Synchronous DRAM

,

H5TC2G63GFR-PBA

Product Description

 

1.Description
The H5TQ2G83GFR-xxC, H5TQ2G63GFR-xxC,H5TQ2G83GFR-xxI, H5TQ2G63GFR-xxI, H5TQ2G83GFRxxL,H5TQ2G63GFR-xxL,H5TQ2G83GFR-xxJ,H5TQ2G63GFR-xxJ are a 2,147,483,648-bit CMOS Double Data
Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large
memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.

2.FEATURES
* This product in compliance with the RoHS directive.
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
9 and 10
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly

8banks
• Average Refresh Cycle (Tcase 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
Commercial Temperature( 0oC ~ 95 oC)
Industrial Temperature( -40oC ~ 95 oC)
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre
Programmable CAS 128M DDR3 Synchronous DRAM H5TC2G63GFR-PBA 0
4.Why choose us?

100% new and originao with Advantage price
High efficiency
Fast Delivery
Professional team service
10 Years Experience Electronic components
Electronic components Agent
Advantage logistic discount
Excellent After-sales Service

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