F59L2G81A-25TG Elite Semiconductor Electronic Integrated Circuits

                                                                                          1.FEATURES

 Voltage Supply: 3.3V (2.7V ~ 3.6V)

 Organization - Memory Cell Array: (256M + 16M) x 8bit - Data Register: (2K + 64) x 8bit

 Automatic Program and Erase - Page Program: (2K + 64) byte - Block Erase: (128K + 4K) byte

 Page Read Operation - Page Size: (2K + 64) bytes - Random Read: 25us (Max.) - Serial Access: 25ns (Min.)

 Memory Cell: 1bit/Memory Cell

 Fast Write Cycle Time - Program time: 350us (Typ.) - Block Erase time: 3.5ms (Typ.)

 Command/Address/Data Multiplexed I/O Port

 Hardware Data Protection - Program/Erase Lockout During Power Transitions

 Reliable CMOS Floating Gate Technology - ECC Requirement: 4bit/512Byte - Endurance: 100K Program/Erase cycles - Data Retention: 10 years  Command Register Operation

 Automatic Page 0 Read at Power-Up Option - Boot from NAND support - Automatic Memory Download

 NOP: 4 cycles

 Cache Program Operation for High Performance Program

 Cache Read Operation

 Copy-Back Operation - EDO mode - OTP Operation - Two-Plane Operation

 Bad-Block-Protect

                                                                    2.GENERAL DESCRIPTION

The device is a 256Mx8bit with spare 16Mx8bit capacity. The device is offered in 3.3V VCC Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2112-Word page in typical 350us and an erase operation can be performed in typical 3.5ms on a 128K-Byte for X8 device block. Data in the page mode can be read out at 25ns cycle time per Word. The I/O pins serve as the ports for address and command inputs as well as data input/output. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the Flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improving the read throughput when consecutive pages have to be streamed out. This device includes extra feature: Automatic Read at Power Up.

                                                                     3.PIN CONFIGURATION (TOP VIEW)

                                                                                         4.Pin Description

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